DACs of the type which are configured in the form of a main DAC and a sub-DAC are well known. For example, such a DAC is disclosed in U.S. Pat. No. 5,969,657 of Dempsey, et al. Another such DAC so configured is disclosed in U.S. Pat. No. 6,567,026 of Gorman, and a DAC somewhat similar to the DAC disclosed in U.S. Pat. No. 6,567,026 is disclosed in U.S. Pat. No. 5,495,245 of Ashe.
Such DACs, in general, comprise a main DAC which comprises one or more main impedance strings formed by a plurality of series connected main impedance elements. The main impedance string or strings are coupled between a first terminal and a second terminal across which a voltage reference is coupled. Typically, each main impedance element of the main impedance string corresponds to the value of one MSB, and the main impedance string defines a plurality of nodes on which voltage signals of progressively increasing selectable values are produced for producing a voltage signal corresponding to the value of the MSBs of the major code part of an input code of a digital input signal. In general, each main impedance element is a resistive element provided by a resistor.
The sub-DAC may be of the type which comprises a secondary impedance string comprising a plurality of series connected secondary impedance elements, and typically, each secondary impedance element corresponds to the value of one LSB. In general, the secondary impedance elements are resistive elements, generally provided by resistors. In general, the secondary impedance string defines a plurality of secondary nodes on which voltage signals of progressively increasing selectable values are produced for producing a voltage signal corresponding to the value of the LSBs of the minor code part of an input code of the digital input signal. The main DAC and the sub-DAC co-operate so that the voltage signal appearing on one of the secondary nodes, in general, as well as including the value of the LSBs also includes the value of the MSBs of the input code. In such cases a secondary switch network is provided for selectively coupling an analogue output terminal of the DAC to an appropriate one of the secondary nodes which provides the analogue output voltage corresponding to the value of the MSBs and the LSBs of the input code.
In general, a main switch network is provided associated with the main impedance string, which has the effect of sliding the secondary impedance string along the main impedance string for progressively increasing or decreasing the value of the voltage signal corresponding to the value of the MSBs supplied from the main DAC to the sub-DAC.
A decoding circuit for decoding input codes of the digital input signal provides switch select signals to the main and secondary switch networks for appropriately operating the switch networks for providing an analogue output voltage on the output terminal corresponding to the values of the input codes of the digital input signal.
Problems arise with such DACs which are configured in the form of a main DAC/sub-DAC configuration at major code transitions when the sub-DAC is moved from interpolating across one main impedance element to the next adjacent main impedance element, in other words, when the value of the MSBs of the input code of the digital input signal changes by one MSB. During major code transitions from one MSB to the next MSB, a relatively large voltage spike develops in the analogue output voltage. Such voltage spikes are commonly referred to as major code transition glitches, and are measured by determining the energy or the magnitude of the voltage spike resulting from the major code transition. Such major code transition glitches cause serious problems where a DAC is being used in a closed-loop control application or where a DAC is being used as a pulse width modulator. In cases where a DAC is used in a control loop application, and the control loop settles around a major code transition, each time the DAC transitions from one major code to the next, a major code transition glitch occurs in the analogue output voltage. Where a transitioning from one LSB to the next LSB occurs without a major code transition occurring, the average analogue output voltage on the output terminal of the DAC is
                    V        1            +              V        2              2    ,where V1 is the voltage on the output terminal before the LSB transition, and V2 is the voltage on the output terminal after the LSB transition. However, when the transition from one LSB to the next LSB occurs at a major code transition, the average analogue output voltage is no longer the average of the voltage before the transition and the voltage after the transition, due to the voltage spike resulting from the major code transition glitch.
Similarly, where such a DAC is used as a pulse width modulator, if the main DAC is cycling around a major code transition, a major code transition glitch occurs twice during each cycle. Accordingly, the analogue output voltage of the DAC is no longer the average of the high and low voltages on each side of the major code transition.
Another problem with major code transition glitches occurring in a DAC which is used in a closed-loop control application is that the glitches themselves may disturb the control loop.
Various attempts have been made to minimise voltage disturbance caused by major code transition glitches. For example, the DAC of Gorman disclosed in U.S. Pat. No. 6,567,026 reduces the voltage spikes of major code transition glitches. However, while such attempts to reduce the voltage disturbance caused by major code transition glitches have undoubtedly been successful to some extent, problems still arise with major code transition glitches in DACs where such DACs are used in closed-loop control circuits and pulse width modulation circuits.
There is therefore a need for a DAC in which major code transition glitches are minimised during operation of the DAC, and there is also a need for a method for minimising major code transition glitches during the operation of a DAC.
The present invention is directed towards providing a DAC, and the invention is also directed towards providing a DAC in which major code transition glitches are minimised. The invention is also directed towards providing a method for minimising major code transition glitches in a DAC.